As particular application, simulations of ULP memory latches used as level-keepers in MTCMOS circuits to maintain information on floating nodes during standby mode demonstrate static power savings of 20% when compared to the best traditional schemes with comparable speed performance. We demonstrate that the ULP diode can be used to realize memory cells that present strongly reduced static power consumption compared to standard SRAM cells and can work under 0.5 V supply voltage. It has been fabricated on 0.18 and 2 μm FD SOI technologies and demonstrated a reduction of leakage currents by four orders of magnitude compared to standard MOS diode implementation.

In particular, a new composite ULP diode is proposed and modelled. These cells take advantage of the possibility to obtain multi-threshold transistors in fully depleted (FD) SOI CMOS with no additional cost. We present new SOI basic circuit cells architectures for ultra-low power (ULP) applications that use transistors in very weak inversion. Ease of technology portability is demonstrated with silicon measurement results in 65 nm, 0.13 μm, and 0.18 μm CMOS technologies. Digital trimming is demonstrated, and assisted one temperature point digital trimming, guided by initial samples with two temperature point trimming, enables TC < 50 ppm/☌ and ☐.35% output precision across all 25 dies. For process spread analysis, 49 dies are measured across two runs, showing the design exhibits comparable spreads in TC and output voltage to existing voltage references in the literature. The proposed design improves energy efficiency by 2 to 3 orders of magnitude while exhibiting better line sensitivity and temperature coefficient in less area, compared to other nanowatt voltage references. Prototype chips in 0.13 μm show a temperature coefficient of 16.9 ppm/☌ (best) and line sensitivity of 0.033%/V, while consuming 2.22 pW in 1350 μm2. This work proposes a voltage reference for use in such ultra-low power systems, referred to as the 2T voltage reference, which has been demonstrated in silicon across three CMOS technologies. This tight power budget places ultra-low power demands on all building blocks in the systems.

Sensing systems such as biomedical implants, infrastructure monitoring systems, and military surveillance units are constrained to consume only picowatts to nanowatts in standby and active mode, respectively.

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